74LS194 - 4-bit Bi-directional Shift Register IC
SKU:
EG0003
Rs. 81

74LS194 - 4-bit Bi-directional Shift Register IC
Rs. 81
The 74LS194 - 4-bit Bi-directional Shift Register IC is a versatile component designed to offer a wide range of features that a system designer might need in a shift register. These features include parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register operates in four distinct modes: Parallel load, Shift right, Shift left, and Inhibit clock. Synchronous parallel loading is achieved by applying the four bits of data and setting both mode control inputs, S0 and S1, to HIGH. The data is then loaded into the corresponding flip-flops and appears at the outputs after the positive transition of the clock input. During this loading process, serial data flow is inhibited. Right shifting is performed synchronously with the rising edge of the clock pulse when S0 is HIGH and S1 is LOW. The serial data for this mode is entered at the shift-right data input. When S0 is LOW and S1 is HIGH, data shifts left synchronously, and new data is entered at the shift-left serial input. Clocking of the flip-flop is inhibited when both mode control inputs are LOW.
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\nPinout Description: 74LS194
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\nIn this context, S1 and S0 are Mode Control Inputs, P0, P1, P2, and P3 are parallel data inputs. DSL and DSR are Serial Data Inputs, CP is Clock Input (Active High Edge), Q0 to Q3 are Parallel Data Output, and MR stands for Master Reset.
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\nPackage Contents
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\n1× 74LS194 - 4-bit Bi-directional Shift Register IC
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Specifications:
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- Operating Voltage: 5V \n
- Supply Current: 23mA \n
- Supply frequency: 20MHz \n
- Parallel inputs and outputs \n
- Four operating modes: Synchronous parallel load, Right shift, Left shift, Do nothing \n
- Positive edge-triggered clocking \n
- Direct overriding clear \n
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\nPinout Description: 74LS194
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\nIn this context, S1 and S0 are Mode Control Inputs, P0, P1, P2, and P3 are parallel data inputs. DSL and DSR are Serial Data Inputs, CP is Clock Input (Active High Edge), Q0 to Q3 are Parallel Data Output, and MR stands for Master Reset.
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\nPackage Contents
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\n1× 74LS194 - 4-bit Bi-directional Shift Register IC
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